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- Sales Rank: #2456637 in Books
- Published on: 1999-06-24
- Original language: English
- Number of items: 1
- Dimensions: 8.98" h x .71" w x 7.01" l, .75 pounds
- Binding: Paperback
- 208 pages
From the Inside Flap
Preface
This book describes the theory and applications of timing verification of application-specific integrated circuits (ASICs). Timing verification is a relatively new concept, which is why most books on digital systems do not cover the issue. This book lays out the fundamental principles of effective timing verification, and it makes good use of the examples that reflect the current issues facing logic designers.
The following items characterize this book:
Timing verification as opposed to functional verification is the primary focus. (Functional simulation has been adequately covered in other books.)Principles and techniques as opposed to specific tools are emphasized. Once designers understand the underlying principles of timing analysis, they can apply them with various timing tools.Design flow for deep-submicron ASICs and FPGA designs are fully covered.Numerous design examples and HDL codes to illustrate the concepts discussed in the book are provided.
This book is to be used for self-study by practicing engineers. Design and verification engineers who are working with ASICs and FPGAs will find the book very useful. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in design courses in timing analysis and related topics.
The material covered in this book requires some understanding of the Electronic Design Automation (EDA) tools and an initial course in logic design.
The book is organized into two parts:
Part I (chapters 1 and 2) introduces the fundamental concepts involved in timing verification. Including clock definitions, multicycle paths, false paths, and phase-locked loops.
Part II (chapters 3 and 4) covers specific timing issues related to ASICs and FPGAs, respectively.
Chapter 1 gives an overview of timing verification and static timing analysis. It contrasts timing verification with functional verification. Typical goals of timing verification in digital systems are presented. This chapter ends with an example of interface timing analysis.
Chapter 2 introduces the concepts of timing analysis with design examples. It specifically discusses such clocking methods as gated clocks, multifrequency clocks, and multiphase clocks. It introduces the concepts of multicycle paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width).
Chapter 3 discusses the deep submicron ASIC design flow and application of timing analysis in the design process. It includes discussion of prelayout and postlayout timing verification. The chapter also discusses behavioral and structural RTL coding for timing, synthesis and timing constraint, and the ASIC sign-off checklist. We make the concepts concrete with numerous examples.
Chapter 4 discusses timing concepts in programmable logic-based designs. It covers design flow, timing parameters, timing analysis, and HDL synthesis and software development systems. We present the most commonly used programmable logic devices (Actel, Altera, and Xilinx) and associated timing issues.
Appendices A, B, and C discuss the EDA timing tools of PrimeTime, Pearl, and TimingDesigner respectively.
Appendix D covers some concepts of transistor-level timing verification.— Farzad Nekoogar
From the Back Cover
79434-7
It's About Time
In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include:
- Clock definitions, multicycle paths, false paths, and phase-locked loops
- Behavioral and structural RTL coding for timing
- Timing analysis of FPGAs
- Pre and Post layout timing analysis
- Synthesis and Timing constraints
- EDA timing tools
Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.
About the Author
FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author of Digital Control Using Digital Signal Processing, published by Prentice Hall PTR.
Most helpful customer reviews
0 of 0 people found the following review helpful.
good book for beginners on FPGA
By Mr. I. Nagy
This book is very good for beginners starting working with FPGAs. Probably ASIC designers need some more, I dont know I am not one of them. Timing analysis is a topic which is unfortunatelly not very well known by lots of engineers working on small/medium size FPGA projects. For them, I would recommend to buy/read this book. It was written 10 years ago for ASICs and now it is still good for FPGAs for learning how to setup simple timing constraints on smaller FPGAs, (for example a PCI, IDE or LPC bus interfaces on a 100kgate Xilinx Spartan-III FPGA) or how to design our logic for higher speed. I knew some things about timing analysis already, so this book taught me a little more. Now I have purchased the "Static Timing Analysis for Nanometer Designs", which is much thicker and more detailed, so I hope I will learn a lot more from that one.
Although these books say ASIC and nanometer-design in their titles, they provide valuable information also for design engineers working with FPGAs, CPLDs or board-level designs.
2 of 2 people found the following review helpful.
Very good book for the beginners
By Art Malik
This is a really good book for the beginners to understand the timing verification in ASIC flow.There are not many books in this area which explain things clearly.Most of them get lost in the syntax and modules of coding. 90% percent of ASIC design is done with synopsys tools and book authors tell more about the tool syntax than why they are there.This book has minimum of tool syntax.It is SIMPLE and that is its greatest quality.Most people who have reviewed the book have given good ratings.The one that is bad must be from an experienced person.This book is not for an expert in this field.
9 of 9 people found the following review helpful.
A "must-have" book for practicing ASIC engineers
By Eugene A. Davis
The book has detailed information on timing issues of ASICs and FPGAs, such as pre and post layout timing analysis. Several comprehensive examples on timing analysis using different available STA tools makes the book a practical guide for verification engineers. The book also covers some RTL coding examples for timing, however it is made solely for timing verification not a book for learning HDL languages, therefore trying to criticize the programming part of the book as in previous review is irrelevant let alone trying to correct spelling.
See all 5 customer reviews...
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